1. Field of the Invention
The present invention relates to a semiconductor device having a metal conducting layer and, more particularly, to a semiconductor device having a metal conducting layer for preventing an exposed metal layer from being oxidized.
2. Description of the Related Art
In semiconductor memory devices, especially, dynamic random access memory (DRAM) devices including a unit cell having one transistor and one capacitor, a gate line acting as a conducting line for transmitting signals to a gate electrode of a transistor and a plurality of gate lines are integrally formed in one direction on a silicon substrate. Lateral surfaces of the gate lines are covered by spacers formed by insulating material for insulating surrounding circuits of the gate lines and for insulating a direct contact (DC) and a buried contact (BC). Generally, the spacers are formed from a silicon nitride (SiN) layer because silicon nitride has good insulating efficiency and does not deteriorate from a thermal process.
According to a conventional spacer forming method using a silicon nitride as a spacer, a gate-insulating layer, a gate conducting layer, and a gate mask layer are sequentially deposited on a silicon substrate and patterned to form a gate line pattern using a photolithography process. Next, a silicon nitride layer is deposited on the silicon substrate having the gate line pattern, and a silicon nitride spacer is formed at a lateral surface of the gate line pattern by etching the silicon nitride layer until exposing a surface of the gate mask layer and the silicon substrate.
According to a conventional method, if an etching selectivity between the silicon nitride layer and the silicon substrate is small, the surface of the silicon substrate can be damaged. The damaged silicon substrate can cause leakage current to flow to a storage capacitor, thereby deteriorating the refresh characteristics of a DRAM.
Recently, a dual spacer having a silicon oxide layer and a silicon nitride layer has been developed. The dual spacer is formed as follows: a gate insulating layer, a gate conducting layer, and a gate insulating mask are sequentially formed on a silicon substrate, then patterned to form a gate line pattern; next, a silicon oxide layer and a silicon nitride layer are sequentially deposited on the silicon substrate having the gate line pattern; and a dual spacer having a silicon oxide layer and a silicon nitride layer is formed at a lateral surface of the gate line pattern by etching the silicon nitride layer until the surface of the silicon oxide layer is exposed.
According to the above method of forming a dual spacer, as an etching selectivity between the silicon nitride layer and the silicon oxide layer is large and the silicon oxide layer acts as an etching blocking layer during etching the silicon nitride layer, the dual spacer is formed without having damage upon removal of the remaining silicon oxide layer.
On the other hand, even though a gate line is generally formed of a conducting layer such as a polysilicon layer and a metal silicide layer, a metal gate line having a pure metal layer such as tungsten and titanium has been developed. When a method of forming a dual spacer is applied to the metal gate line, after forming a gate line pattern having the pure metal layer, when a silicon oxide is deposited the exposed metal layer may be oxidized. The undesirable oxidation at the surface of the metal layer can lower an effective surface area of a conducting line, increase the resistance of the conducting line, and result in the gate line pattern not having a vertical profile.
Therefore, it is highly desirable to provide a method of manufacturing a semiconductor device having a metal conducting layer to prevent an exposed metal layer from being oxidized when a silicon oxide layer is deposited to insulate a conducting layer such as a pure metal layer. Further, it is highly desirable to provide a method of manufacturing a semiconductor device including a metal conducting layer having a vertical profile.
A method of manufacturing a semiconductor device having a metal conducting layer is provided, the method includes the steps of: forming a metal conducting layer pattern having the metal conducting layer on a semiconductor substrate, a portion of the metal conducting layer being partially exposed on the semiconductor substrate; loading the semiconductor substrate having the metal conducting layer pattern into a reaction chamber; flowing a first silicon source gas into the reaction chamber; and forming a silicon oxide layer on the semiconductor substrate having the metal conducting layer pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber.
According to an embodiment of the present invention, the step of flowing the first silicon source gas is performed within an incubation period during which silicon is not deposited onto the metal conducting layer. The step of flowing the first silicon source gas is performed within about 60 seconds. The step of flowing the first silicon source gas is performed at a pressure of the reaction chamber of about 0.001 torr to about 500 torr and at a temperature of the semiconductor substrate of about 500xc2x0 C. to 1000xc2x0 C. The step of flowing the first silicon source gas into the reaction chamber is performed within a flow rate of the silicon source gas of 100 sccm. The metal conducting layer is one of a tungsten layer and a titanium layer. The first silicon source gas is selected from the group consisting of SiH4, Si2H6, and DCS (dichloro silane). The second silicon source gas is selected from the group consisting of SiH4, Si2H6, and DCS (dichloro silane).
Preferably, the method further includes an oxygen source gas in the step of flowing the first silicon source gas. The silicon source gas is flowed into the reaction chamber in advance of the oxygen source gas. The oxygen source gas is N2O or O2.
A method of manufacturing a semiconductor device having a metal conducting layer is also provided, the method includes the steps of: forming a gate pattern having the metal conducting layer on a semiconductor substrate; loading the semiconductor substrate having the gate pattern into a reaction chamber; flowing a first silicon source gas into the reaction chamber; and forming a silicon oxide layer on the semiconductor substrate having the gate pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber; forming a silicon nitride layer on the silicon oxide layer; and forming spacers on lateral surfaces of the gate pattern by etching the silicon nitride layer until exposing the silicon oxide layer.
According to an embodiment of the present invention, the step of flowing the first silicon source gas is performed within an incubation period during which silicon is not deposited onto the metal conducting layer. The reaction chamber is a single wafer type reaction chamber. The step of flowing the first silicon source gas is performed within about 60 seconds at a pressure within of the reaction chamber of about 0.001 torr to about 500 torr and at a temperature of the semiconductor substrate of about 500xc2x0 C. to 1000xc2x0 C., and within a flow rate of the first silicon source gas of 100 sccm. The gate pattern is formed by sequentially depositing a gate insulating layer, a polysilicon layer, a metal conducting layer, and a mask layer on the silicon substrate.
Preferably, the method further includes an oxygen source gas in the step of flowing the first silicon source gas. The oxygen source gas is N2O or O2. The silicon source gas is flowed into the reaction chamber in advance of the oxygen source gas. The first silicon source gas and the second silicon source are selected from the group consisting of SiH4, Si2H6, and DCS (dichloro silane).